1. Field of the Invention
The present invention relates to image display apparatus, and for example, can be applied to an active matrix image display apparatus including an organic EL (Electro Luminescence) element. The present invention enables a wiring pattern on an insulating substrate to be efficiently arranged compared to the related art by having a dummy region arranged at an outermost periphery of a display unit as a scanning line coupling region or a pitch conversion region, or by having a power supply scanning line commonly used by a pixel circuit of odd-numbered lines and a pixel circuit of even-numbered lines.
2. Description of Related Art
In recent years, development of the active matrix image display apparatus using the organic EL element is advancing. The image display apparatus using the organic EL element is an image display apparatus that utilizes a luminous phenomenon of an organic thin-film that emits light by application of electric field. The organic EL element can be driven at an application voltage of smaller than or equal to 10[V]. Therefore, this type of image display apparatus can reduce the power consumption. The organic EL element is a self-luminous element. Therefore, this type of image display apparatus may not include a backlight device, and thus can have lighter weight and can be thinned. The organic EL element has a characteristic in that a response speed is fast or about a few μseconds. Therefore, this type of image display apparatus has a characteristic in that a residual image barely generates when displaying a moving image.
Specifically, the active matrix image display apparatus using the organic EL element arranges a pixel circuit including the organic EL element and a drive circuit for driving the organic EL element in a matrix form to form a display unit. This type of image display apparatus drives each pixel circuit by the signal line drive circuit and the scanning line drive circuit arranged at the periphery of the display unit by way of the signal line and the scanning line arranged in the display unit to display the desired image.
Regarding the image display apparatus using the organic EL element, Japanese Patent Application Laid-Open No. 2007-310311 discloses a method of configuring a pixel circuit using two transistors. Therefore, the configuration can be simplified according to the method disclosed in Japanese Patent Application Laid-Open No. 2007-310311. Japanese Patent Application Laid-Open No. 2007-310311 also discloses a configuration of correcting the variation in the threshold voltage of the drive transistor for driving the organic EL element and the variation in the mobility. Therefore, degradation in image quality caused by the variation in the threshold value of the drive transistor and the variation in the mobility can be prevented according to the configuration disclosed in Japanese Patent Application Laid-Open No. 2007-310311.
FIG. 14 is a block diagram showing an image display apparatus disclosed in Japanese Patent Application Laid-Open No. 2007-310311. The image display apparatus 1 has a display unit 2 formed on an insulating substrate of glass and the like. The image display apparatus 1 has a signal line drive circuit 3 and a scanning line drive circuit 4 formed at the periphery of the display unit 2.
The display unit 2 is formed by arranging a pixel circuit 5 in a matrix form, where the organic EL element arranged in the pixel circuit 5 forms a pixel (PIX) 6. In an image display apparatus for color image, one pixel is formed by a plurality of sub-pixels of red, green, and blue, and thus the display unit 2 is configured by sequentially arranging the pixel circuits 5 for red, for green, and for blue respectively configuring the sub-pixels of red, green, and blue in the case of the image display apparatus for color image.
The signal line drive circuit 3 outputs a drive signal Ssig for the signal line to a signal line DTL arranged in the display unit 2. More specifically, the signal line drive circuit 3 sequentially latches image data D1 input in a raster scanning order and allocates the image data D1 to the signal line DTL, and then performs the digital-analog conversion process in the data scan circuit 3A. The signal line drive circuit 3 processes the digital-analog conversion result, and generates the drive signal Ssig. The image display apparatus 1 thereby sets a tone of each pixel circuit 5 in a so-called line sequential manner.
The scanning line drive circuit 4 outputs a write signal WS and a drive signal S to the scanning line WSL for write signal and the scanning line DSL for power supply, respectively, arranged in the display unit 2. The write signal WS is a signal for ON/OFF controlling a write transistor arranged in each pixel circuit 5. The drive signal DS is a signal for controlling the drain voltage of the drive transistor arranged in each pixel circuit 5. The scanning line drive circuit 4 processes a predetermined sampling pulse SP with a clock CK and generates the write signal WS and the drive signal DS in a write scan circuit (WSCN) 4A and a drive scan circuit (DSCM) 4B.
FIG. 15 is a connection diagram showing the configuration of the pixel circuit 5 in detail. The pixel circuit 5 has a cathode of the organic EL element 7 set to a predetermined negative side voltage, where such negative side voltage is set to the voltage of the earth line in the example of FIG. 15. The pixel circuit 5 has an anode of the organic EL element 8 connected to a source of the drive transistor Tr2. The drive transistor Tr2 is an N-channel transistor including TFT. The pixel circuit 5 has the drain of the drive transistor Tr2 connected to the power supply scanning line DSL, and the power supply drive signal DS is provided to the scanning line DSL from the scanning line drive circuit 4. The pixel circuit 5 then current drives the organic EL element 8 using the drive transistor Tr2 of the source-follower circuit configuration.
The pixel circuit 5 has a retention capacity Cs arranged between the gate and the source of the drive transistor Tr2, and the gate side voltage of the retention capacity Cs is set to the voltage of the drive signal Ssig by the write signal WS. As a result, the pixel circuit 5 current drives the organic EL element 8 with the drive transistor Tr2 by the gate-source voltage Vgs corresponding to the drive signal Ssig. In FIG. 15, a capacity Ce1 is a stray capacitance of the organic EL element 8. In the following description, the capacity Ce1 has a sufficiently large capacity compared to the retention capacity Cs, and the parasitic capacitance of the gate node of the drive transistor Tr2 is sufficiently small compared to the retention capacity Cs.
In other words, the pixel circuit 5 has the gate of the drive transistor Tr2 connected to the signal line DTL by way of the write transistor Tr1 that ON/OFF operates by the write signal WS. The write transistor Tr1 is an N-channel transistor including TFT. The signal line drive circuit 3 switches the tone setting voltage Vsig and the threshold voltage correction fixed voltage Vofs at a predetermined timing, and outputs the drive signal Ssig. The threshold voltage correction fixed voltage Vofs is a fixed voltage used to correct the variation in the threshold voltage of the drive transistor Tr2. The tone setting voltage Vsig is a voltage instructing the light emission luminance of the organic EL element 8, and is a voltage obtained by adding the threshold voltage correction fixed voltage Vofs to the tone voltage Vin. The tone voltage Vin is a voltage corresponding to the light emission luminance of the organic EL element 8. The tone voltage Vin is generated for every signal line DTL by performing digital-analog conversion process on the image data D1 allocated to each signal line DTL.
As shown in FIG. 16, the pixel circuit 5 has the write transistor Tr1 set to the OFF state by the write signal WS during the light emission period of light emitting the organic EL element 8 (FIG. 16A). The pixel circuit 5 has the power supply voltage Vcc supplied to the drive transistor Tr2 by the power supply drive signal DS during the light emission period (FIG. 16B). The pixel circuit 5 thus light emits the organic EL element 8 with the drive current Ids corresponding to the gate-source voltage Vgs (FIGS. 16D and 16E) of the drive transistor Tr2 or the inter-terminal voltage of the retention capacity Cs during the light emission period.
In the pixel circuit 5, the power supply drive signal DS reduces to a predetermined fixed voltage Vss at time point t0 when the light emission period ends (FIG. 16B). The fixed voltage Vss is a voltage sufficiently low to function the drain of the drive transistor Tr2 as a source, and is a voltage lower than the cathode voltage of the organic EL element 8.
As shown in FIG. 18, in the pixel circuit 5, the accumulated charges of the organic EL element 8 side end of the retention capacity Cs flow out to the scanning line via the drive transistor Tr2. As a result, in the pixel circuit 5, the source voltage Vs of the drive transistor Tr2 reduces to substantially the voltage Vss (FIG. 16E), and the organic EL element 8 stops light emission. Furthermore, in the pixel circuit 5, the gate voltage Vg of the drive transistor Tr2 lowers in conjunction with the lowering of the source voltage Vs (FIG. 16D).
The pixel circuit 5 has the write transistor Tr1 switched to the ON state by the write signal WS at the following predetermined time point t1 (FIG. 16A), and the gate voltage Vg of the drive transistor Tr2 is set to the threshold voltage correction fixed voltage Vofs set to the signal line DTL (FIGS. 16C and 16D). As shown in FIG. 19, the pixel circuit 5 has the gate-source voltage Vgs of the drive transistor Tr2 set to substantially the voltage Vofs-Vss. The pixel circuit 5 has the voltage Vofs-Vss set to a voltage greater than the threshold voltage Vth of the drive transistor Tr2 setting the voltages Vofs, Vss.
Thereafter, in the pixel circuit 5, the drain voltage of the drive transistor Tr2 reduces to the power supply voltage Vcc by the drive signal DS at time point t2 (FIG. 16B). As shown in FIG. 20, in the pixel circuit 5, the charging current Ids flows in from the power supply Vcc to the organic EL element 8 side end of the retention capacity Cs through the drive transistor Tr2. As a result, the voltage Vs on the organic EL element 8 side end of the retention capacity Cs gradually rises in the pixel circuit 5. In this case, in the pixel circuit 5, the current Ids flowing into the organic EL element 8 through the drive transistor Tr2 is used only in charging the capacity Ce1 and the retention capacity Cs of the organic EL element 8, and as a result, only the source voltage Vs of the drive transistor Tr2 is merely raised without light emitting the organic EL element 8.
In the pixel circuit 5, the flowing in of the charging current Ids through the drive transistor Tr2 stops when the inter-terminal voltage of the retention capacity Cs becomes the threshold voltage Vth of the drive transistor Tr2. Therefore, in this case, the rise of the source voltage Vs of the drive transistor Tr2 stops when the potential difference of both ends of the retention capacity Cs becomes the threshold voltage Vth of the drive transistor Tr2. The pixel circuit 5 thus discharges the inter-terminal voltage of the retention capacity Cs through the drive transistor Tr2, and sets the inter-terminal voltage of the retention capacity Cs to the threshold voltage Vth of the drive transistor Tr2.
When a sufficient time for setting the inter-terminal voltage of the retention capacity Cs to the threshold voltage Vth of the drive transistor Tr2 has elapsed and time point t3 is reached, the pixel circuit 5 has the write transistor Tr1 switched to the OFF state by the write signal, as shown in FIG. 21 (FIG. 16A). Subsequently, as shown in FIG. 22, the voltage of the signal line DTL is set to the tone setting voltage Vsig (=Vin+Vofs).
The pixel circuit 5 has the write transistor Tr1 set to the ON state in the following time point t4 (FIG. 16A). As shown in FIG. 23, the pixel circuit 5 has the gate voltage Vg of the drive transistor Tr2 set to the tone setting voltage Vsig, and the gate-source voltage Vgs of the drive transistor Tr2 set to the voltage in which the threshold voltage Vth of the drive transistor Tr2 is added to the tone voltage Vin. The pixel circuit 5 can effectively avoid the variation of the threshold voltage Vth of the drive transistor Tr2 and drive the organic EL element 8, and can prevent degradation in image quality due to variation in the light emission luminance of the organic EL element 8.
When setting the gate voltage Vg of the drive transistor Tr2 to the tone setting voltage Vsig, the pixel circuit 5 has the gate of the drive transistor Tr2 connected to the signal line DTL for a constant period while holding the drain voltage of the drive transistor Tr2 at the power supply voltage Vcc. The variation in the mobility μ of the drive transistor Tr2 is thereby also corrected in the pixel circuit 5.
In other words, when the write transistor Tr1 is set to the ON state and the gate of the transistor Tr2 is connected to the signal line DTL with the inter-terminal voltage of the retention capacity Cs set to the threshold voltage Vth of the drive transistor Tr2, the gate voltage Vg of the drive transistor Tr2 gradually rises from the fixed voltage Vofs and is set to the tone setting voltage Vsig.
In the pixel circuit 5, the write time constant for the rise of the gate voltage Vg of the drive transistor Tr2 is set short compared to the time constant for the rise of the source voltage Vs by the drive transistor Tr2.
In this case, when the write transistor Tr1 is ON operated, the gate voltage Vg of the drive transistor Tr2 rapidly rises to the tone setting voltage Vsig (Vofs+Vin). In time of the rise of the gate voltage Vg, the source voltage Vs of the drive transistor Tr2 does not fluctuate if the capacity Ce1 of the organic EL element 8 is sufficiently large compared to the retention capacity Cs.
However, if the gate-source voltage Vgs of the drive transistor Tr2 becomes greater than the threshold voltage Vth, the current Ids flows in from the power supply Vcc via the drive transistor Tr2, and the source voltage Vs of the drive transistor Tr2 gradually rises. As a result, in the pixel circuit 5, the inter-voltage voltage of the retention capacity Cs discharges from the drive transistor Tr2, and the rising speed of the gate-source voltage Vgs lowers.
The discharge speed of the inter-terminal voltage changes according to the ability of the drive transistor Tr2. More specifically, the discharge speed becomes faster the larger the mobility μ of the drive transistor Tr2.
As a result, the pixel circuit 5 is set such that the inter-terminal voltage of the retention capacity Cs lowers for the drive transistor Tr2 of large mobility μ, and the variation in the light emission luminance due to the variation of the mobility is corrected. The amount of lowering of the inter-terminal voltage related to the correction of the mobility μ is shown as ΔV in FIG. 16, FIG. 23, and FIG. 24.
In the pixel circuit 5, the write signal WS falls at time point t5 after the elapse of the correction period of the mobility. As a result, the pixel circuit 5 starts the light emission period, and light emits the organic EL element 8 by the drive current Ids corresponding to the inter-terminal voltage of the retention capacity Cs, as shown in FIG. 24. When the light emission period starts, the gate voltage Vg and the source voltage Vs of the drive transistor Tr2 rise by a so-called boot strap circuit in the pixel circuit 5. Ve1 in FIG. 24 is the voltage of the amount of rise.
Therefore, the pixel circuit 5 executes the preparation of the process of correcting the threshold voltage of the drive transistor Tr2 during a period in which the gate voltage of the drive transistor Tr2 is lowered to the voltage Vss from time point t0 to time point 2. In the following period from time point t2 to time point t3, the inter-terminal voltage of the retention capacity Cs is set to the threshold voltage Vth of the drive transistor Tr2, and the threshold voltage of the drive transistor Tr2 is corrected. From time point t4 to time point t5, the mobility of the drive transistor Tr2 is corrected and the tone setting voltage Vsig is sampled.
Japanese Patent Application Laid-Open No. 2007-133284 proposes a configuration of executing a process of correcting the variation in the threshold voltage of the drive transistor Tr2 over plural times. According to the configuration of the disclosure in Japanese Patent Application Laid-Open No. 2007-133284, sufficient time can be given to the correction of the variation of the threshold voltage even if higher accuracy is achieved and the time assigned to tone setting of the pixel circuit is reduced. Therefore, degradation in image quality due to the variation of the threshold voltage can be prevented even when the accuracy is increased.
Therefore, a display apparatus capable of maintaining high image quality even when the accuracy is increased is obtained with a simple configuration by applying the method disclosed in Japanese Patent Application Laid-Open No. 2007-133284 to the method disclosed in Japanese Patent Application Laid-Open No. 2007-310311.
FIG. 25 is a time chart of the pixel circuit that can be assumed when the method disclosed in Japanese Patent Application Laid-Open No. 2007-133284 is applied to the method disclosed in Japanese Patent Application Laid-Open No. 2007-310311, in comparison to FIG. 16.
In this case, the tone setting voltage Vs of each pixel circuit 5 connected to the signal line DTL is output to the signal line DTL with the threshold voltage correction fixed voltage Vofs in between. In the pixel circuit 5, the write signal WS is intermittently raised in correspondence to the drive of the signal line DTL, and the inter-terminal voltage of the retention capacity Cs is discharged through the drive transistor Tr2 in a plurality of periods. Specifically, in the example of FIG. 25, the variation correction of the threshold voltage of the drive transistor Tr2 is executed in four periods of periods T1, T2, T3, and T4, and then the mobility correction process and the tone setting process are executed in period T5. In FIG. 25, VD is a vertical synchronization signal.
FIG. 26 is a plan view showing an image display apparatus disclosed in Japanese Patent Application Laid-Open No. 2007-133284. The image display apparatus 1 has the display unit 2 formed at substantially the middle of the insulating substrate 11 of glass and the like. A signal line integrated circuit 13 and a scanning line integrated circuit 14 configuring the signal line drive circuit 3 and the scanning line drive circuit 4, respectively, are arranged at the periphery of the display unit 2. The integrated circuits 13, 14 are mounted on flexible wiring substrates 15 and 16, and then connected to the insulating substrate 11 through the flexible wiring substrates 15 and 16, and the flexible wiring substrates 15 and 16 are bent and arranged on the rear surface side of the insulating substrate 11. The image display apparatus 1 has a flexible wiring substrate 17 for supplying power and the like connected at four corners of the insulating substrate 11.
FIG. 27 is a plan view showing the area between the display unit 2 and the scanning line integrated circuit 14 shown with reference number A in FIG. 26 in a partially enlarged manner. The display unit 2 has a dummy region arranged at the outermost periphery of the effective display region, where equalization of the thermal profile is achieved when annealing the drive transistor Tr2 and the like using a dummy pixel circuit 5D arranged in the dummy region. Therefore, in the display unit 2, a region excluding the dummy region is the effective display region.
The display unit 2 is formed such that the pixel pitch in the vertical direction is 300 [μm]. The scanning line integrated circuit 14 is arranged with an electrode at an extremely small pitch, smaller than the pitch obtained by dividing the pixel pitch of the display unit 2 by the number of scanning lines assigned to one pixel circuit 5. Similarly, the signal line integrated circuit 13 is also arranged with an electrode at a pitch extremely short with respect to the pixel pitch of the display unit 2.
In the image display apparatus 1 of the related art, a pitch conversion region is arranged at the periphery of the display unit 2, where the pitch of the wiring pattern P by the electrode pitch of the integrated circuits 14, 15 is enlarged to the pitch of the signal line DTL, and the scanning lines DSL and WSL and connected to the signal line DTL, and the scanning lines DSL and WSL in the pitch conversion region.